1. Field of the Invention
This invention relates to a speed controller of a motor such as a capstan motor used in a video tape recorder, and so forth.
2. Description of the Related Art
A speed controller of a motor which detects a rotating speed of a motor by a tachometer and controls feed power to the motor by its detection signal has widely been used for a capstan motor of a Video tape recorder, and so forth. However, such a speed controller effects only proportional-integral control or differential control but has not been able to sufficiently suppress fluctuations of the rotating speed due to torque disturbances.
To solve such a problem, a speed controller of a motor having extremely high robustness against the torque disturbances has been proposed in JP-A-62-89487, JP-A-62-89488 and U.S. Pat. No. 4,821,168. Furthermore, JP-A-62-210881 and U.S. Pat. No. 4,755,729 propose a speed controller of a motor which drastically reduces the number of necessary memories and reduces also the calculation quantity necessary within one detection cycle of speed detection means. In other words, a speed control system is constituted by a rotation sensor for generating an A.C. signal having a period in accordance with the rotating speed of a motor, speed detection means for detecting a plurality of times detection operations per round of the motor by the A.C. signal of the rotation sensor, compensation means for generating a control signal on the basis of the detection signal of the speed detection means, and driving means for driving the motor in accordance with the control signal of the compensation means. Furthermore, the compensation means includes rotation error detection means for obtaining a rotation error responsive to the detection signal of the speed detection means, memory means for storing 4 or more memory values, memory output value generation means for generating a memory output value by the use of at least one memory value stored in the memory means, synthetic error generation means for generating a synthetic error by synthesizing a plurality of rotation errors of the rotation error detection means, renewing and storing means for renewing and storing substantially sequentially the memory values of the memory means by a renewed value corresponding to a value obtained by calculating and synthesizing the memory output value of the memory output value generation means and the synthetic error of the synthetic error generation means, and control signal generation means for generating a control signal by calculating and synthesizing the memory output value of the memory output value generation means and the rotation error of the rotation error detection means, wherein the control signal generation means generates a new control signal whenever the speed detection means generates a new detection signal, the renewing and storing means renews substantially one memory value whenever the speed detection means obtains Q new detection signals (where Q is an integer of 2 or more), and the operations of at least the memory output value generation means and renewing and storing means are substantially different from each other with respect to the timing of the detection signal of the speed detection means. In this way, the reference accomplishes an economical speed controller of a motor having high performance.
The speed controller of the motor disclosed in JP-A-62-210881 and U.S. Pat. No. 4,755,729 can certainly reduce drastically the number of necessary memories but in order to accomplish more economically this high performance speed controller, it is essentially necessary to further reduce the number of necessary memories. Since the operation of the synthetic error generation means includes a large number of multiplication operations, it has been necessary in the past to use an expensive high speed multiplier so as to make high speed calculation and to complete predetermined calculations within the detection cycle of the tachometer. In other words, various limitations have yet been left unsolved in connection with the construction and operation speeds of hardwares for accomplishing the compensation means.